Computer Engineering — UC San Diego — 2026

Hasaan Haq

> Embedded Systems DeveloperFirmware EngineerSystems ProgrammerHardware Bring-Up Engineer
Open to opportunities
San Diego, CA
Sys.InfoLive
RoleEmbedded Systems Developer
StackC · C++ · Python · SV
FocusFirmware · RTOS · Bring-Up
LocationSan Diego, CA

I build and validate embedded systems: board bring-up, firmware drivers, and the test infrastructure that proves a system works before it ships.

Recent work spans a regulated electrophysiology simulator at Boston Scientific, STM32/NXP firmware bring-up, and production test automation for over a thousand embedded boards.

Languages
CC++PythonAssemblySystemVerilog
Embedded
STM32NXPARMRTOSLinux
Interfaces
UARTSPII2CCANGPIO
Debug
GDBOscilloscopesLogic Analyzers
Jun — Sept 2026
Software Development Engineer InternBoston ScientificWaltham, MA

Eliminated nondeterministic results in a multithreaded Qt simulation application and built Python/Bash automation to validate hardware-to-simulator behavioral fidelity for electrophysiology systems.

Sept — Dec 2025
Firmware Engineer InternRoot AccessRemote / New York, NY

Performed board bring-up across STM32 and NXP platforms, validated CLI-generated firmware for register and HAL-layer defects, and reverse-engineered embedded IDE build systems.

Aug — Oct 2025
Embedded Systems DeveloperGelTech, LLCSan Diego, CA

Enhanced an internal testing GUI with configurable parameters and built custom Python diagnostics for hardware validation.

Oct 2022 — Sept 2024
Embedded Systems Engineering InternCalpak USA, Inc.Los Angeles, CA

Reverse-engineered UART/SPI communication on an STM32F429 plethysmograph and built Python tooling to automate flashing and validation across 1,000+ production boards.

U1
Autonomous Plant-Health Rover
Raspberry Pi 5ROS 2PythonOAK-D Lite

Autonomous rover navigating GPS waypoints, running plant-health inspection routines with computer vision and soil sensors.

U2
SHA-256 Bitcoin Hashing Accelerator
SystemVerilogModelSimQuartusFPGA

Serial and parallel RTL datapaths for SHA-256 hashing, evaluating 16 nonce candidates in parallel with self-checking testbenches.

U3
Custom OS Kernel in Nachos
JavaVirtual MemoryTLB

Thread scheduling, syscall interfaces, and demand-paged virtual memory using the clock replacement algorithm.

U4
CMOS Digital Circuit Design & Timing Analysis
Cadence VirtuosoCMOSSTA

Transistor-level CMOS gates and flip-flops with propagation delay and setup/hold timing characterization.

04 — Contact

Let's build something.

Open to embedded and firmware roles for Fall 2026.